1. Field of the Invention
The present invention relates generally to fabrication of metal oxide semiconductor field effect transistors (MOSFETs), and, more particularly, to MOSFETs that achieve improved carrier mobility through the incorporation of strained silicon.
2. Related Technology
MOSFETs are a common component of integrated circuits (ICs). FIG. 1 shows a cross sectional view of a conventional MOSFET device. The MOSFET is fabricated on a silicon substrate 10 within an active region bounded by shallow trench isolations 12 that electrically isolate the active region of the MOSFET from other IC components fabricated on the substrate 10.
The MOSFET is comprised of a gate 14 that is separated from a channel region 16 in the substrate 10 by a thin gate insulator 18 such as silicon oxide or silicon oxynitride. A voltage applied to the gate 14 controls the availability of carriers in the channel region 16 through formation of an inversion layer in the channel. To minimize the resistance of the gate 14, the gate 14 is typically formed of a doped semiconductor material such as polysilicon.
The source and drain of the MOSFET comprise deep source and drain regions 20 formed on opposing sides of the channel region 16. The deep source and drain regions 20 are implanted by ion implantation subsequent to the formation of a spacer 22 around the gate 14, which serves as a mask during implantation to define the lateral positions of the deep source and drain regions 20 relative to the channel region 16.
Source and drain silicides 24 are formed on the deep source and drain regions 20 and are comprised of a compound comprising the substrate semiconductor material and a metal such as cobalt (Co) or nickel (Ni) to reduce contact resistance to the deep source and drain regions 20. The deep source and drain regions 20 are formed deeply enough to extend beyond the depth to which the source and drain silicides 24 are formed. The gate 14 likewise has a silicide 26 formed on its upper surface. A gate structure comprising a polysilicon material and an overlying silicide is sometimes referred to as a polycide gate.
The source and drain of the MOSFET further comprise shallow source and drain extensions 28. As dimensions of the MOSFET are reduced, short channel effects resulting from the small distance between the source and drain cause degradation of MOSFET performance. The use of shallow source and drain extensions 28 rather than deep source and drain regions near the ends of the channel 16 helps to reduce short channel effects. The shallow source and drain extensions 28 are implanted after the formation of a protective layer 30 around the gate 14 and over the substrate, and prior to the formation of the spacer 22. The gate 14 and the protective layer 30 act as an implantation mask to define the lateral position of the shallow source and drain extensions 28 relative to the channel region 16. Diffusion during subsequent annealing causes the shallow source and drain extensions 28 to extend slightly beneath the gate 14.
One option for increasing the performance of MOSFETs is to enhance the carrier mobility of the MOSFET semiconductor material so as to reduce resistance and power consumption and to increase drive current, frequency response and operating speed. A method of enhancing carrier mobility that has become a focus of recent attention is the use of silicon material to which a tensile strain is applied. “Strained” silicon may be formed by growing a layer of silicon on a silicon germanium substrate. The silicon germanium lattice is more widely spaced on average than a pure silicon lattice because of the presence of the larger germanium atoms in the lattice. Since the atoms of the silicon lattice align with the more widely spaced silicon germanium lattice, a tensile strain is created in the silicon layer. The silicon atoms are essentially pulled apart from one another. The amount of tensile strain applied to the silicon lattice increases with the proportion of germanium in the silicon germanium lattice.
The tensile strain applied to the silicon lattice increases carrier mobility. Relaxed silicon has six equal valence bands. The application of tensile strain to the silicon lattice causes four of the valence bands to increase in energy and two of the valence bands to decrease in energy. As a result of quantum effects, electrons effectively weigh 30 percent less when passing through the lower energy bands. Thus the lower energy bands offer less resistance to electron flow. In addition, electrons encounter less vibrational energy from the nucleus of the silicon atom, which causes them to scatter at a rate of 500 to 1000 times less than in relaxed silicon. As a result, carrier mobility is dramatically increased in strained silicon as compared to relaxed silicon, offering a potential increase in mobility of 80% or more for electrons and 20% or more for holes. The increase in mobility has been found to persist for current fields of up to 1.5 megavolts/centimeter. These factors are believed to enable a device speed increase of 35% without further reduction of device size, or a 25% reduction in power consumption without a reduction in performance. An example of a MOSFET incorporating a strained silicon layer is shown in FIG. 2. The MOSFET is fabricated on a substrate comprising a silicon germanium layer 32 grown on a silicon layer 10. An epitaxial layer of strained silicon 34 is grown on the silicon germanium layer 32. The MOSFET uses conventional MOSFET structures including deep source and drain regions 20, shallow source and drain extensions 28, a gate oxide layer 18, a gate 14 surrounded by spacers 30, 22, source and drain silicides 24, a gate silicide 26, and shallow trench isolations 12. The channel region of the MOSFET includes the strained silicon material, which provides enhanced carrier mobility between the source and drain.
FIG. 3 shows an example of a strained silicon MOSFET formed on a silicon-on-insulator (SOI) substrate. In this example, the MOSFET is formed on an SOI substrate that comprises a silicon germanium layer 32 provided on a dielectric substrate 36. The SOI substrate may be formed by a buried oxide (BOX) method or by bonding the oxidized surface of a silicon wafer to a silicon germanium layer formed on a second silicon wafer, and removing the silicon portion of the second wafer by fracturing after hydrogen implantation. In one alternative to the SOI structure of FIG. 3, strained silicon FinFETs comprised of monolithic silicon germanium FinFET bodies having strained silicon grown thereon may be formed from the silicon germanium SOI substrate.
One detrimental consequence of the use of strained silicon in MOSFETs is that the threshold voltage Vt that is required to create an inversion layer in the MOSFET channel is reduced by approximately 200 mV. The threshold voltage shift is the result of changes in the conduction bands of strained silicon compared to relaxed silicon, and the effects are therefore manifested primarily in NMOS devices. While a reduced threshold voltage is desirable in general because it reduces power consumption, the asymmetric reduction of NMOS threshold voltage relative to PMOS threshold voltage presents control issues in circuits such as CMOS circuits that employ both NMOS and PMOS devices. Also, a reduction in threshold voltage can produce an exponential increase in the leakage current that flows through the device in the off state, and hence the power consumption is detrimentally raised.
It is therefore desirable to compensate for the NMOS threshold voltage shift. The conventional approach to providing threshold voltage compensation is to increase the doping in the channel region. However, increased channel region doping causes increased Coulomb scattering and degrades electron mobility, thus decreasing device performance and detracting from the advantages that the use of strained silicon is meant to provide.
Therefore the performance provided by conventional strained silicon MOSFET technology is constrained by conflicting requirements. While strained silicon provides significant carrier mobility enhancement, strained silicon also reduces the NMOS threshold voltage, and this latter effect has heretofore required compensation through techniques that degrade the carrier mobility that the strained silicon is meant to provide. Thus the advantages achieved by incorporating strained silicon into MOSFET designs are partly offset by the disadvantages resulting from the conventional techniques that must be employed to compensate for the threshold voltage shift.